1. Technical Field
The invention relates generally to verification of electronic circuit designs, and particularly to validation of multi-voltage circuit designs against predefined rules.
2. Prior Art
Electronic Design Automation (EDA) is a process which uses computer programs to design, simulate, and test electronic circuits before they are fabricated. Using these tools detects and corrects design flaws before fabrication of the silicon device. Test before fabrication processes save manufacturers millions of dollars in Non-Recoverable Engineering (NRE) costs.
An automated circuit design process includes several steps, beginning with providing a Hardware Description Language (HDL) description (a high level description) of a circuit design. Several HDLs are commonly available, e.g. Verilog and VHDL. The HDL description may also be in the form of a Register Transfer Logic (RTL) code. A computer-implemented process converts the high-level description into a netlist, which is a structural representation of the electronic circuit that specifies details on (i) cells that constitute the circuit and (ii) details on the wire connections (nets) of different pins of cells. A netlist does not describe the physical location of the cells on a silicon chip. The netlist creation process is followed by a placement process, which finds a location for each cell on a circuit board or silicon chip. The locations are specified, typically, in two dimensional (i.e., x, y) spatial coordinates on the circuit board or silicon chip. Subsequently, the netlist and the cell location information are used to perform a wire routing process which generates a wire geometry within a data structure for connecting pins together. This information is converted into a description of a mask for fabrication of the actual silicon chip. The description may be provided in available languages such as GDS2.
After certain stages of the automated circuit designing process, the intermediate resulting information needs to be verified for potential errors.
FIG. 1 is a flowchart illustrating a generic method for verification and modification of a multi-voltage circuit design. Step 102 inputs a Hardware Description Language (HDL) description of the multi-voltage design and multi-voltage information. The HDL describes the circuit design in blocks and sub-blocks, which may also be referred to as design elements. Each design element may in itself be a semiconductor device, for example a transistor. A design element may also be a combination of two or more semiconductor devices. Some examples of HDLs that may be used include the commonly available languages Verilog and VHDL. The HDL description may also be in the form of an RTL code. Multi-voltage information comprises design partitioning information and voltage state information, as further detailed in conjunction with FIGS. 2A and 2B. The voltage state information is further detailed in conjunction with FIG. 3.
Step 104 checks the multi-voltage circuit design for certain pre-defined rules. Based on the rule checking step 106 modifies the multi-voltage circuit design.
Step 108 compiles the HDL description of the multi-voltage circuit design to logically validate the design. A typical compilation process converts the HDL into several design objects. The design objects may correspond to each design element, the voltage connections to the design element, the logical connections between design elements, and the like.
Step 110 performs the simulation process, which applies voltage vectors at the inputs of the circuit design. These voltage vectors generate logic waveforms in the circuit design. The logic waveforms in a digital circuit have certain specific values, for example, 0, 1, X and Z in case of Verilog. The voltage vector values varying with time change the resulting logic waveforms, which are observed and recorded. Step 112 generates the simulation results representing the behavior of the circuit for certain parameters. The behavior is then compared with the desired results from the circuit.
Electronic circuits are becoming increasingly complex and consequently encountering new problems of power management. Contemporary electronic circuits consume significant amounts of power, which is undesirable because of heating problems and limited battery life of electronic devices. Therefore, managing power for optimal use is highly desired.
One way of optimizing power consumption is by partitioning multi-voltage electronic circuits and managing power for these partitions separately. In a multi-voltage design, different functional units of the electronic circuit are operated at different voltages at different times. For example, in case of an electronic circuit for a mobile phone, the functional units for audio, processing and camera are different. When the audio unit is being operated, the camera unit may be switched off and the processing unit may be operated at 1.0 V. In another case, when the camera unit is being operated, the audio unit may be switched off and the processing unit may be operated at 1.2 V. A mobile phone circuit design element may have voltage states such as active, standby, sleep, shutdown, etc.
Multi-voltage electronic circuits as described above have complex designs comprising several elements or cells which are characterized by their connections to various power rails carrying different voltages which may change with time.
FIGS. 2A and 2B are schematics of an example design element 202 having input 204 and output 206 connections that carry logic waveforms having particular values, for example 0, 1, X or Z in Verilog. Design element 202 is connected to six voltage rails; a VDD rail 208, a SLPP rail 210, a SLPN rail 212, a VBBP rail 214, a VBBN rail 216, and a VSS rail 218.
VDD rail 208 is a driving rail that provides power to design element 202. SLPP rail 210 and SLPN rail 212 are sleep rails connected to the gates of header transistor 209 and of footer transistor 211 to apply positive, zero, or negative voltage differences between the gate and the source of the transistors and thereby cut off leakage current between rails 208 and 218. VBBP rail 214 and VBBN rail 216 are body bias rails for Positive Metal Oxide Semiconductor (PMOS) transistor 215 and for Negative Metal Oxide Semiconductor (NMOS) transistor 217 respectively, which are applied to the bulk connection and can either be forward or reverse biased to control threshold voltage (Vt).
Other design elements may have connections to fewer or more voltage rails.
The values of voltages on the rails connected to design element 202 determine its voltage state, of which there may be several. An example design element 202 may have four voltage states: active state, shutdown state, standby state and sleep state. During the active state, VDD rail 208 operates on an allotted functional voltage value, and design element 202 can perform all its functions. During shutdown state, VDD rail 208 is either turned off, or the value of voltage in VDD rail 208 is below a shutdown threshold voltage value. However, during this state the voltage value on VDD rail 208 is not zero. Standby state is a low power state which expects a quick wakeup. During standby state, the voltage value on VDD rail 208 is between a maximum standby threshold voltage value and a minimum standby threshold voltage value. State retention in memory elements of a design element 202 is essential. Typically, in standby state all the clocks are gated, i.e. deactivated by a gating design element such as an AND gate (not shown). Standby state may have multiple grades which progressively turn off more circuitry. Entering and leaving standby state involves gradually turning off/on of clocks, PLLs, and voltages. Sleep state is a variation of shutdown state, and is also called power gating. SLPP 210 and/or SLPN 212 are controlled with a negative Vgs (V gate-source) to cut off design element 202 from VDD 208 and VSS 218.
However, complex voltage designs of electronic circuits make verification of the designs extremely difficult. The above-mentioned generic verification process is insufficient for validation of multi-voltage circuit designs. Existing methods for checking multi-voltage electronic circuit designs suffer from one or more of the following problems. First, the verification tools for electronic circuits are not voltage aware, i.e. they do not consider voltage as a parameter for performing the verification, although in reality voltage is a key parameter. Therefore, any design verification tool without consideration of voltage is susceptible to lead to faulty designs. Second, the existing methods of verification of multi-voltage circuit designs do not provide the required accuracy. Third, the existing verification methods are slow and therefore require long time to generate results. There exists, therefore, a need for a verification method of electronic circuit designs that overcomes the limitations of existing systems.